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Hardware & Compute

chiplet

nounAlso: chiplets, multi-die design, die-to-die interconnect, UCIe, tile

In plain wordsOne of several smaller chips that are made separately and then joined inside a single package to work as one processor, which is cheaper than making one giant chip and lets makers reuse parts.

  1. A die built as one building block of a multi-die package: each chiplet carries a portion of a system — compute cores, cache, input/output or memory interfaces — and talks to its neighbors over short, dense die-to-die links, instead of everything being integrated on one monolithic chip. Splitting a design improves manufacturing yield (a defect ruins only a small die), allows each function to use the best process nodeprocess node, n.: The label for a generation of chip-making technology, like '3 nanometer'. Smaller numbers mean newer, denser chips, but the number no longer measures any actual part of the chip. — leading-edge for compute, older for input/output or analog — enables reuse across products, and lets designs exceed the reticle limit of roughly 850 mm² that caps a single die. Examples include AMD's EPYC and Instinct MI300 processors, Intel's Ponte Vecchio and Nvidia's Blackwell GPU, which joins two reticle-sized dies with a 10 TB/s link. The costs are extra power and latency for crossing between dies and dependence on advanced packagingadvanced packaging, n.: Ways of joining several chips very closely inside one package — side by side on a silicon base or stacked on top of each other — so they act almost like one bigger chip.. The UCIe standard (2022) aims to let chiplets from different vendors interoperate.

Origin

Earliest use is uncertain. Patent searches find 'chiplet' as early as 1969 in other senses, and in roughly its present sense in IBM patent applications published in late 2000; a coinage often credited to John Wawrzynek of the University of California, Berkeley (c. 2006, RAMP project) therefore came later. Multi-chip modules are older still. Chiplets went mainstream with AMD's second-generation EPYC processors (2019); the Universal Chiplet Interconnect Express (UCIe) consortium formed in March 2022.

Related

See also
  • advanced packagingadvanced packaging, n.: Ways of joining several chips very closely inside one package — side by side on a silicon base or stacked on top of each other — so they act almost like one bigger chip.
  • process nodeprocess node, n.: The label for a generation of chip-making technology, like '3 nanometer'. Smaller numbers mean newer, denser chips, but the number no longer measures any actual part of the chip.
  • high-bandwidth memoryhigh-bandwidth memory, n.: Very fast memory made by stacking memory chips on top of each other and placing them right next to the processor, so AI chips can be fed data quickly enough.
  • interconnectinterconnect, n.: The wiring and networking that connect chips to each other — inside a server, across a data center, or within a single chip — so they can share data and work as one.
  • wafer-scale enginewafer-scale engine, n.: A single giant processor made from nearly a whole dinner-plate-sized silicon wafer instead of the small chips normally cut from it, so data rarely has to leave the chip.
  • Moore's lawMoore's law, n.: Gordon Moore's prediction that chipmakers could pack twice as many transistors onto a chip roughly every two years — a pace that for decades made computers steadily faster and cheaper, and has slowed but not stopped.
Contrast with
  • wafer-scale enginewafer-scale engine, n.: A single giant processor made from nearly a whole dinner-plate-sized silicon wafer instead of the small chips normally cut from it, so data rarely has to leave the chip.

Mentioned in

Moore's lawMoore's law, n.: Gordon Moore's prediction that chipmakers could pack twice as many transistors onto a chip roughly every two years — a pace that for decades made computers steadily faster and cheaper, and has slowed but not stopped., interconnectinterconnect, n.: The wiring and networking that connect chips to each other — inside a server, across a data center, or within a single chip — so they can share data and work as one., process nodeprocess node, n.: The label for a generation of chip-making technology, like '3 nanometer'. Smaller numbers mean newer, denser chips, but the number no longer measures any actual part of the chip., semiconductor foundrysemiconductor foundry, n.: A factory company that manufactures chips designed by other companies. Taiwan's TSMC, the largest, makes nearly all of the world's most advanced AI chips., advanced packagingadvanced packaging, n.: Ways of joining several chips very closely inside one package — side by side on a silicon base or stacked on top of each other — so they act almost like one bigger chip., wafer-scale enginewafer-scale engine, n.: A single giant processor made from nearly a whole dinner-plate-sized silicon wafer instead of the small chips normally cut from it, so data rarely has to leave the chip.